1. Field of the Invention
The present invention relates to a level shifter, which level-converts an input signal and then outputs the resulting signal, a semiconductor integrated circuit, and an information processing system. In particular, it is related to a level shifter, which converts an input low-level signal into a high-level signal, a semiconductor integrated circuit, and an information processing system.
2. Description of the Prior Art
In recent years, computer motherboards are equipped with multiple devices such as ASIC, microprocessors, memories, and peripheral circuits, and an increasing number of microcomputers are designed to fulfill desired functions. Particularly, since operation with low amounts of power consumption and at high frequencies is required with the ASIC and microprocessors, amplitude of the supply voltage to be internally utilized has been designed to decreased. For example, given a 2.5 V internal supply voltage, this voltage is inclined to decrease to 1.8 V, 1.5 V and 1.2 V in the future.
In contrast, there are many devices such as peripheral circuits that operate at 3.3 V where input/output of data between each device is executed at 3.3 V based on JEDEC system interface standards or the like. Consequently, the condition where the peripheral circuits operate at 3.3 V and the ASIC and microprocessor operate at a different voltage of 2.5 V has been increasing. Accordingly, the ASIC and microprocessor are equipped with input/output buffers with a 3.3 V supply voltage in order to level shift by the voltage difference. In other words, the ASIC and microprocessor run on two power supplies, where an internal power supply is 2.5 V and an input/output buffer power supply is 3.3 V.
Such level shifting function-equipped conventional input/output buffer is illustrated in FIG. 24. The conventional input/output buffer (level shifter) is one that converts a 2.5 V amplitude input signal SIN to the level of a 3.3 V amplitude output signal SOUT, and is configured from an inverter INV1, 3.3 V-tolerant P-channel MOS transistors MP1 and MP2, and 3.3 V-tolerant N-channel MOS transistors MN1 and MN2. Hereafter, a MOS transistor is simply referred to as a transistor.
The inverter INV1 has a CMOS structure, which is configured from a P-channel transistor and an N-channel transistor, and inverts the 2.5 V amplitude input signal SIN so as to output an inverted input signal SINB with an amplitude of 2.5 V. The transistor MP1 has a 3.3 V supply voltage VDD applied to its source, its drain connected to the transistor MP2 gate, and its gate connected to the transistor MP2 drain. The transistor MP2 has a 3.3 V supply voltage VDD applied to its source, and the output signal SOUT with amplitude of 3.3 V is output from its drain. The transistor MP1 has the input signal SIN applied to its gate, its drain connected to the transistor MP1 drain, and its source connected to a ground. The transistor MP2 has the inverted input signal SINB applied to its gate, its drain connected to the transistor MP2 drain, and its source connected to a ground.
Next, the operation of the above-configured level shifter is described. To begin with, when the input signal SIN with a 2.5 V amplitude is at an “H” level, the transistor MN1 turns on, and at the same time since the inverted input signal SINB becomes at an “L” level, the transistor MN2 turns off. Accordingly, the transistor MP2 turns on whereas the transistor MP1 turns off. Therefore, the “H” level output signal SOUT of 3.3 V amplitude is output from this level shifter.
In contrast, when the input signal SIN is at the “L” level, the transistor MN1 turns off, and at the same time since the inverted input signal SINB becomes the “H” level, the transistor MN2 turns on. Accordingly, the transistor MP2 turns off whereas the transistor MP1 turns on. Therefore, the “L” level output signal SOUT is output from this level shifter.
It should be noted that disclosed in Japanese Patent Application Laid-open No. Hei 11-239051 is a conventional negative logic level shifter where the output signal SOUT differs from the configuration described above.
The conventional level shifter mentioned above operates normally when the “H” level of the inverted input signal SINB is substantially higher than the threshold voltage Vt (typically 0.7 V) of the transistor MN2 gate voltage, and the resistance between the source and the drain of the off transistor MP2 is sufficiently smaller than that of the on transistor MN2. However, since the transistors MN1 and MN2 are not fully turned on when the “H” level of the inverted input signal SINB drops until near the threshold voltage Vt of the transistor MN2 gate voltage, the resistance between the source and the drain of the transistor MN2 that is insufficiently turned on abruptly increases to a value matching that of the Off transistor MP2, whereby driving the subsequent transistors MP1 and MP2 is no longer possible. As a result, even when the input signal SIN is at the “L” level, the output signal SOUT stays at the “L” level, namely it can no longer decrease to 0 V, where the level shifter is unable to operate normally.
Input and output waveforms and voltages are described based on FIG. 25 through FIG. 30. It should be noted that in FIG. 25 through FIG. 30, the vertical axis represents input signal voltage (V) and the horizontal axis represents time (nS (nanoseconds)). Furthermore, the gate width of the transistors MP1 and MP2 is set as 10 μm and the gate width of the transistors MN1 and MN2 is set as 30 μm.
It can be understood from the waveform of FIG. 25 that with an input signal amplitude up to 2.0 V, level shifting to 3.3 V is possible without any change in the duty ratio. From the waveforms of FIG. 26 and FIG. 28, however, it can be understood that the duty ratio cannot be maintained regardless that level shifting has been performed as the input voltage drops from 1.5 V to 1.35 V.
Moreover, when the input signal voltage drops and becomes 1.2 V and 1.0 V, the output signals change at only near 3 V as illustrated in FIG. 29 and FIG. 30, respectively. In other words, the output signals no longer drop to 0 V. As a result, it is the same as if the level shifter actually outputs an “H” level signal, thereby becoming unable to transmit the input signal changes to the subsequent circuit.
Furthermore, with a first level shifter, it is evident that it takes long for the output signal to change and the level to reach a stable level since the input signal has changed, in other words, the response speed is slow, and particularly the slower as the input voltage drops more. For example, when the input signal is 2.0 V, as illustrated in FIG. 25, approximately 0.5 nanoseconds has lapsed from the time when the input signal begins rising to when the output voltage reaches a stable level; however, it is evident that when the input signal is 1.4 V, as illustrated in FIG. 27, approximately 1.5 nanoseconds has lapsed from the time when the input signal begins rising to when the output voltage reaches a stable level.
Moreover, since the transistors MN1 and MN2 are driven in the non-saturation region (insufficient ON state), if noise is superimposed at the input signal SIN and/or ground lines, resistance between the sources and drains of the transistors MN1 and MN2 abruptly fluctuates. As a result, there are cases where the ON-current widely varies and the capability of driving the subsequent transistors MP1 and MP2 is hindered. In this case, the waveform of the output signal SOUT becomes significantly irregular.
Furthermore, since the transistors MN1 and MN2 are driven in the non-saturation region, the ON-current values thereof are extremely small. As a result, it takes time for the gates of the subsequent transistors MP1 and MP2 to charge and discharge, and also to reach a stable level for the output signal SOUT potential since the input signal SIN is asserted from “L” level to “H” level or deasserted from “H” level to “L” level. Accordingly, the maximum frequency of the signal that is capable of operating the level shifter of this example becomes limited. Furthermore, during the transition period from when the input signal SIN has changed to when SOUT reaches a stable level, both the transistors MP1 and MN1 are not off, or both the transistors MP2 and MN2 are not off. Therefore, a large current, namely a flow-through current flows from the supply voltage VDD to the ground GND via the transistors MP1 and MN1 or the transistors MP2 and MN2. Consequently, the fact that it takes time to reach a stable level for the output signal SOUT potential since the input signal SIN is asserted or deasserted namely the transition time is long means that the time of the flow-through current flowing is long, causing power consumption to increase.
In this regard, as illustrated in FIG. 37, it can be understood from the waveform of the power supply current supplied to the first level shifter that a current continually flows during the period from when the input signal has changed to when the output signal reaches a stable level, and it can also be understood from the fact that the consumed power is determined from the amount and flowing period of the current that the first level shifter requires a large amount of power. It should be noted that the power supply current waveform of FIG. 37 is used as an example of one with an input signal of 1.4 V for the first level shifter. Furthermore, the power supply current waveform graph applies input voltage V to the left side vertical axis, time nS (nanoseconds) to the horizontal axis, and current mA to the right side vertical axis, as with the graphs in FIG. 38 to FIG. 40.